The present invention relates to a probe card configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory components located on a wafer, in parallel. The probe card configuration has a carrier board for bringing up electric signal lines from a test system and has contact-making needles for producing electrical connections with contact areas on the circuits to be tested.
Current DRAM (Dynamic Random Access Memory) chips are tested with expensive memory test systems. Test programs for checking the functional suitability of the memory chips are used on these testers. In this case, signals with exactly defined voltage levels are applied to the semiconductor circuits to be tested at exactly defined times. During the checking of the read function of the DUT (Device Under Test), it is also possible to read signals coming into the test instrument from the DUT at precisely defined times and to compare them with expected signal values.
Because of the high frequencies at which current memory modules operate, for example 200 to 300 MHz in the case of DDR (Double Data Rate) DRAMs and 400 to 800 MHz in the case of Rambus DRAMs, the these chips specify highly accurate signals. For example, in the case of DDR memories, signal specifications of the order of magnitude of 500 ps are common. The production or memory test systems that are used therefore have to meet extremely high technical requirements, which leads to correspondingly high production and testing costs. At present, DRAM test instruments that meet the aforementioned conditions cost several millions of dollars each. All of this causes the testing costs to be up to 30% of the production costs in the case of the highest frequency memory modules.
Functional testing of the memory modules is carried out both at the wafer level, and following separation, at the module level. Nowadays, at the wafer level, the basic function of the memory chip is usually checked in relatively low frequency range of about 10 to 100 MHz. The higher-frequency tests are then carried out following mounting in the encapsulated state, on specific module testers.
In principle, it would be desirable to carry out a high-speed test on the memory components as early as at the wafer level, since then the functional test is carried out at a time which is beneficial from the value creation point of view, so that there is a great potential for cost savings.
However, high-frequency tests at the wafer level are possible only to a limited extent at present, which is mainly attributable to the large geometric dimensions of the test configuration. From the pin electronics of the tester as far as the components to be tested via the test head, the probe card configuration has to bridge dimensions in the order of magnitude of 10 cm to 1 m. This is virtually impossible with adequate accuracy and with high parallelism at frequencies of 200 MHz to 1 GHz.
U.S. Pat. No. 6,064,213 discloses a probe card configuration. Published German Patent application DE 198 26 314 A1 discloses an arrangement for testing a plurality of integrated circuits in parallel. The arrangement has a carrier board to bring up electrical signal lines of a test system and has a plurality of mounts to accommodate the integrated circuits to be tested. This is where the invention begins.
It is accordingly an object of the invention to provide a probe card configuration for testing a plurality of integrated circuits on a wafer in parallel and a method of using the probe card configuration to test the plurality of the integrated circuits on the wafer which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a probe card configuration for testing a plurality of integrated circuits in parallel using a test system. The probe card configuration includes a carrier board for receiving electrical signal lines of the test system. The carrier board defines a plane. The probe card configuration includes contact-making needles for producing electrical connections with contact areas on the integrated circuits to be tested. The contact-making needles are for connecting to the electrical signal lines of the test system to produce signal paths between the test system and the integrated circuits to be tested. The probe card configuration also includes a plurality of active modules configured on the carrier board. Each one of the plurality of the active modules is assigned to one of the integrated circuits to be tested in parallel. Each one of the plurality of the active modules is inserted into ones of the signal paths that are between the test system and the assigned one of the integrated circuits to be tested. The plurality of the active modules are configured at least partly overlapping in a direction at right angles to the plane of the carrier board.
In accordance with an added feature of the invention, each one of the plurality of the integrated circuits has a longest extent; each one of the plurality of the active modules has a longest extent; and the longest extent of each one of the plurality of the active modules is greater than the longest extent of the assigned one of the integrated circuits to be tested.
With the foregoing and other objects in view there is provided, in accordance with the invention, a probe card configuration for testing a plurality of integrated circuits in parallel using a test system. The probe card configuration includes a carrier board for receiving electrical signal lines of the test system. The carrier board defines a plane. The probe card configuration includes contact-making needles for producing electrical connections with contact areas on the integrated circuits to be tested. The contact-making needles are for connection with the electrical signal lines of the test system to produce signal paths between the test system and the integrated circuits to be tested. The probe card configuration also includes a plurality of active modules configured on the carrier board. Each one of the plurality of the active modules is assigned to one of the integrated circuits to be tested in parallel. Each one of the plurality of the active modules is inserted into ones of the signal paths that are between the test system and the respective assigned one of the integrated circuits to be tested. Each one of the plurality of the active modules has a longest extent. The longest extent of each one of the plurality of the active modules is configured non-parallel with the plane of the carrier board.
In accordance with an additional feature of the invention, the longest extent of each one of the plurality of the active modules is configured at right angles with respect to the plane of the carrier board.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for the testing a plurality of integrated circuits on a wafer in parallel, which includes steps of: providing the probe card configuration according to one of the above described embodiments; making contact between a first group of the integrated circuits to be tested on the wafer and the contact-making needles; performing a test routine with the first group of the integrated circuits to be tested; making contact between a second group of the integrated circuits to be tested on the wafer and the contact-making needles, the second group of the integrated circuits being located disjunct with respect to the first group of the integrated circuits; performing a test routine with the second group of the integrated circuits to be tested; configuring the integrated circuits to be tested on the wafer in a regular rectangular grid form having main directions at right angles to one another; configuring the first group of the integrated circuits and the second group of the integrated circuits to extend along the main directions of the grid; performing the step of making contact between the first group of the integrated circuits and the contact-making needles such that a given one of the integrated circuits is located between two of the integrated circuits of the first group in one of the main directions, and the given one of the integrated circuits is not tested in parallel with the first group of the integrated circuits; and performing the step of making contact between the second group of the integrated circuits and the contact-making needles such that another given one of the integrated circuits is located between two of the integrated circuits of the second group in one of the main directions, and the other given one of the integrated circuits is not tested in parallel with the second group of the integrated circuits. As a result, a minimum number of testing operations is needed in order to test all the circuits on a wafer.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for testing a plurality of integrated circuits on a wafer in parallel, which includes steps of: providing the probe card configuration according to one of the above described embodiments; making contact between a first group of the integrated circuits to be tested on the wafer and the contact-making needles; performing a test routine with the first group of the integrated circuits to be tested; making contact between a second group of the integrated circuits to be tested on the wafer and the contact-making needles, the second group of the integrated circuits being located disjunct with respect to the first group of the integrated circuits; performing a test routine with the second group of the integrated circuits to be tested; configuring the integrated circuits to be tested on the wafer in a regular rectangular grid form having diagonals; and configuring the first group of the integrated circuits and the second group of the integrated circuits to extend along the diagonals of the grid.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a configuration for testing a plurality of integrated circuits in parallel. The configuration includes a test system having electrical signal lines and a carrier board receiving the electrical signal lines of the test system. The carrier board defines a plane. The configuration includes a plurality of mounts for accommodating the plurality of the modules to be tested. The plurality of the mounts receive the electrical signal lines of the test system. The plurality of the mounts are connected to the electrical signal lines of the test system for producing signal paths between the test system and the modules to be tested. The configuration includes a plurality of active modules configured on the carrier board. Each one of the plurality of the active modules are assigned to one of the modules to be tested in parallel. Each one of the plurality of the active modules are inserted into ones of the signal paths that are between the test system and the assigned one of the modules to be tested. The plurality of the active modules are configured to at least partly overlap in a direction at right angles to the plane of the carrier board.
According to the invention, a generic probe card configuration is provided for testing a plurality of integrated circuits on a wafer in parallel. The probe card configuration includes a plurality of active modules that are arranged on a carrier board, are each assigned to one of the circuits to be tested in parallel, and are each inserted into the signal path between the test system and the associated circuit to be tested.
By means of the active modules, for example low frequency test signals from a relatively slow test system can be actively transformed into high-frequency test signals for high-speed tests on the modules to be tested. In general, the active modules permit lower requirements to be placed on the intelligence and/or the speed of the test system, since such functions can be performed by the active modules belonging to the probe card configuration.
It is preferable for the active modules to be arranged at least partly overlapping, based on a direction perpendicular to the plane of the carrier board. This has the advantage that, even in the case of relatively large dimensions of the active modules, the area effectively needed per active module remains small. In particular, even circuits arranged beside one another on the wafer can also be tested in parallel if the active modules have a larger dimension than the circuits to be tested. In this case, in particular, in edge regions of the configuration, it is often not necessary for all of the active modules to be arranged overlapping.
Alternatively, the active modules are arranged, at least partly, with their longest extent not in parallel, but preferably at right angles to the plane of the carrier board. This also achieves the situation where the active modules need a smaller effective area on the probe card configuration.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a test configuration and test method for the parallel testing of a plurality of integrated circuits, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
The invention is to be explained in more detail below using an exemplary embodiment in conjunction with the drawings. In each case, only the elements essential to an understanding of the invention are illustrated. In this case: